1. Field of the Invention
The present invention relates to a semiconductor integrated circuit for cryptographic process and an encryption algorithm alternating method, which are capable of achieving improvement of a security protection performance of cryptography.
2. Description of the Related Art
In recent years, according to the development of communication infrastructure such as the Internet, etc., a concern for the electronic commerce which can arrange the settlement of accounts of the money on the network is caused and the cryptographic technology is needed as the important technology. Such cryptographic technology should be employed since secrecy of the contents can be ensured by coding an amount of money, approved contents, etc. in communication even in the case that an outsider intercepts the contents of the electronic commerce in the middle of communication. Nevertheless, there has been no absolutely reliable cryptographic technology at present.
FIG. 1 is a schematic block circuit diagram showing a semiconductor integrated circuit for cryptographic process in the prior art. In the semiconductor integrated circuit for cryptographic process, the same key is employed as the locking key and the unlocking key and also the transmitter and the receiver possess commonly the same key. A basic algorithm will be explained hereinbelow.
A text input which is formed as a block of 64 bit (8 byte) is divided into two right and left 4 byte (32 bit), and then one of two 4 byte is input into a function F portion 101. In this function F portion 101, randomizing process is executed by using the key data, then an exclusive logical sum of randomized data and the other of 4 byte is calculated by an exclusive logical sum (EXOR, indicated by an encircled + mark) 3, and then the exclusive logical sum is output to a succeeding function F portion 101. In this manner, the above randomizing process is repeated in unit of 4 byte by using a function F and key information. In the end, the right and left 4 byte are synthesized to obtain an 8-byte coded text. Decoding process can be executed by carrying out the above steps sequentially in reverse order.
FIG. 2 shows a DES (Data Encryption Standard) which is employed as a standard at present. This DES is employed in the function F portion 101 in FIG. 1. In FIG. 2, a unit E executes process of expanding 32 bit into 48 bit. Each of steps S1 to S8 denotes a table which converts 6 bit into 4 bit. In addition, a unit P is a processing portion which rearranges the bit order of 32 bit. In this way, in the DES, permutation of data is performed at the first round of the input portion and the final output portion.
Like the above, in the semiconductor integrated circuit for cryptographic process in the prior art, since an encryption algorithm is fixed, it is possible to decrypt the cryptography by virtue of full search of keys. In order to make the full search of keys impossible in practical use, a time consumed in the cryptographic process may be enhanced by increasing an amount of hard ware of the semiconductor integrated circuit for cryptographic process, e.g., increasing the round number in FIG. 1, etc.
However, if an amount of the hard ware of the semiconductor integrated circuit for cryptographic process is increased in order to make the decryption impossible in practical use, first there has been such a problem that an occupied area of the semiconductor integrated circuit is increased inevitably because a considerable amount of the hard ware is needed. Second, there has been another problem that it takes a lot of time to execute the process in normal use because a considerable amount of the hard ware is also needed.